The present disclosure relates generally to a slew rate control system, and more specifically, to a slew rate control system based on feathered clock signals.
Slew rate is an important specification in double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices. In particular, the adjustment and control of the slew rate can increase signal integrity and mitigate undesirable crosstalk effects at memory links between the memory controller and the dual in-line memory module (DIMM) of the DDR SDRAM.
Conventional schemes for controlling the slew rate are based on a full-rate architecture scheme. The full-rate architecture scheme utilizes a full-rate clock signal along with a plurality of delay lines to generate a delay signal that delays the output edges of the data signal transmitted on the data lines. The use of a full-rate clock signal, however, requires the need to re-time each individual delay line. Consequently, the full-rate architecture scheme increases the components required to control the slew rate and causes timing uncertainty at the driver output.